Challenges and opportunities of steep-slope electron devices
Professeur Marco Pala, DPIA, University of Udine, Italy
Mardi 2 Juin 2026 à 13h30
Résumé :
Nowadays, the most relevant challenge in micro/nanoelectronics is to find an optimal trade-off between electrical performance and power consumption. The most straightforward strategy to reduce the dynamic power in integrated circuits, namely the scaling of the supply voltage VDD, is no longer a viable path for circuits based on Si-MOSFETs, which must obey the Boltzmann limit of the sub-threshold swing S. Alternative device architectures promising to break the Boltzmann limit and to achieve sub-threshold swings smaller than 60 mV/dec typically suffer from low drive currents and high sensitivity to traps.
This talk will discuss recent advances in the development of efficient steep-slope devices by discussing experimental results on broken-gap Ga/Sb vertical nanowire tunnel-FETs providing high on-state current Ion and steep S at a low VDD = 0.3 V. The physics of these devices will be analyzed thanks to 3-D full quantum self-consistent simulations adopting the non-equilibrium Green’s functions methodology.
Finally, the presentation will focus on recent device designs proposing innovative cold-source FETs based on the density-of-states engineering of their source regions, enabled by the unique electronic properties of 2D lamellar materials.
Biographie:
Marco Pala received the physics degree and the PhD in electronical engineering from the University of Pisa, Italy in 2000 and 2004, respectively. From 2004 to 2005 he was post-doc at CEA-LETI, Grenoble, France.
He joined the CNRS as research scientist in 2005 at IMEP-LAHC, Grenoble. From 2016 to 2023 he was with the Centre for Nanoscience and Nanotechnology (C2N), Palaiseau, France, where he was the leader of the computational electronics group. From 2023 he is professor at the University of Udine, Italy. His main research interests concern the electronic and transport properties of nanoscale devices. Recently, he worked on quantum transport calculations based on ab-initio methods to assess the use of new materials in nanoelectronics. He is co-author of 99 papers in peer-reviewed journals and 53 proceedings in international conferences.
Nowadays, the most relevant challenge in micro/nanoelectronics is to find an optimal trade-off between electrical performance and power consumption. The most straightforward strategy to reduce the dynamic power in integrated circuits, namely the scaling of the supply voltage VDD, is no longer a viable path for circuits based on Si-MOSFETs, which must obey the Boltzmann limit of the sub-threshold swing S. Alternative device architectures promising to break the Boltzmann limit and to achieve sub-threshold swings smaller than 60 mV/dec typically suffer from low drive currents and high sensitivity to traps.
This talk will discuss recent advances in the development of efficient steep-slope devices by discussing experimental results on broken-gap Ga/Sb vertical nanowire tunnel-FETs providing high on-state current Ion and steep S at a low VDD = 0.3 V. The physics of these devices will be analyzed thanks to 3-D full quantum self-consistent simulations adopting the non-equilibrium Green’s functions methodology.
Finally, the presentation will focus on recent device designs proposing innovative cold-source FETs based on the density-of-states engineering of their source regions, enabled by the unique electronic properties of 2D lamellar materials.
Biographie:
Marco Pala received the physics degree and the PhD in electronical engineering from the University of Pisa, Italy in 2000 and 2004, respectively. From 2004 to 2005 he was post-doc at CEA-LETI, Grenoble, France.
He joined the CNRS as research scientist in 2005 at IMEP-LAHC, Grenoble. From 2016 to 2023 he was with the Centre for Nanoscience and Nanotechnology (C2N), Palaiseau, France, where he was the leader of the computational electronics group. From 2023 he is professor at the University of Udine, Italy. His main research interests concern the electronic and transport properties of nanoscale devices. Recently, he worked on quantum transport calculations based on ab-initio methods to assess the use of new materials in nanoelectronics. He is co-author of 99 papers in peer-reviewed journals and 53 proceedings in international conferences.
Partenaires
Polytechnic Department of Engineering and Architecture, University of Udine, via delle Scienze 206, 33100 Udine, Italy
Documents à télécharger
Infos date
Mardi 2 Juin 2026 à 13h30
Infos lieu
Salle BELLEDONNE et VIDEOCONFERENCE