Verilog-A

Mercredi 10 Novembre 2021 à 13:30 

1) General Overview
   Importance of Verilog-A
   History and prospects
   Advantages and limitations

2) How to model in Verilog-A
   Language overview
   Basic component examples
   Verilog-A with Cadence Spectre

3) Example: Noise and dynamic variability
   Trap-related noise in MOSFETs
   Frequency domain modeling
   Time domain modeling