PhD Defense of Donghyun KIM

Published on November 28, 2023

A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail

PhD Defense December 5, 2023

Defense of doctoral thesis of Donghyun KIM, for the University Grenoble Alpes, speciality " NANO ELECTRONIC ET NANO TECHNOLOGIES ", entitled :

Room 316 2511, Sejong-ro, Jochiwon-eup, Sejong-si
Republic of Korea 30019 Sejong-si

Characterization and modelling of MOS transistors from advanced technologies (FDSOI, nanowire, GaN HEMT, LTPS…)

Donghyun KIM

Tuesday, december 5, 2023

Keywords :

Charactertization,Microelectronics,MOSFET

Abstract :

In this study, the electrical characterization and modeling of various electronic devices based on MOSFET structure were carried out.

Electrical characterization of 2-vetically stacked Nanosheet FETs on FDSOI by using statistical analysis.
NSFETs contained various dimensions were investigated for both NFET and PFET. Each device was measured in a lot of dies over 170 ea. Electrical parameters were extracted using various methods (Y-function and LW function, etc). The correlation of different electrical parameters (Ion, Ioff, SS, mobility, and mobility degradation factors) was investigated. The standard deviation of each electrical parameter was utilized for the interpretation of Pelgrom's law.
GaN HEMT analysis down to cryogenic temperature
A detailed electrical characterization and transistor parameter extraction on 200 mm CMOS compatible GaN/Si HEMTs was performed down to deep cryogenic temperatures. The main transistor parameters (threshold voltage Vth, low-field mobility μ0, subthreshold swing SS, source-drain series resistance Rsd) were extracted in linear region using the Y-function and the Lambert-W function methods for gate lengths down to 0.1 μm. The Y-function method was also employed in saturation region for the extraction of the saturation velocity. The results indicate that these GaN/Si HEMT devices demonstrate a very good functionality down to very low temperature with improvement of mobility and subthreshold slope. It was also shown by TLM analysis that the source-drain series resistance Rsd is more limited by the contact resistance than by the 2DEG access region resistance as temperature lowered.
Electrical characteristics and Trap profiling in LTPS TFT comparing to on rigid and flexible substrates.
The carrier transport of p-type low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrate has been intensively studied and compared to that on glass substrate in order to improve device performance. To investigate the origin of carrier transport on different substrates, temperature dependent characterizations are carried out for electrical device parameters such as threshold voltage (VTH ), subthreshold swing (SS), on-current (Ion) and effective carrier mobility (μeff). The poly-Si grain size Lgrain and the barrier height EB between grain boundaries are well known to be the main parameters to determine transport in polycrystalline silicon and can be extracted based on the polycrystalline mobility model. However, our systemic studies show that it is not grain size but EB that has more influence on the degradation of LTPS TFT on flexible substrates. The EB of flexible substrate is roughly 18 times higher than glass substrate whereas grain size is similar for both devices on different substrates. Compared to the LTPS TFT on glass substrate, higher EB degrades approximately 24 % of Ion, 30 % of SS and 21 % of μeff on the flexible substrate at room temperature. From low frequency noise (LFN) analysis, it is observed that the total trap density (Nt) for flexible substrate is up to four times higher than that of glass substrate, which also supports the high value of EB in the device fabricated on the flexible substrate.

Jury members:

Francis BALESTRA , RESEARCH DIRECTOR - CNRS Alpes Delegation: Supervisor
Jae Woo LEE, ASSOCIATE PROFESSOR - Korea University : Supervisor
Ji-Woon YANG , FULL PROFESSOR - Korea University : Examiner
Quentin RAFHAY, ASSOCIATE PROFESSOR HDR - Grenoble Alpes University : Examiner
Hyun Suk KIM , FULL PROFESSOR , Dongguk University : Reviewer
Pascal MASSON, PROFESSOR OF UNIVERSITY - Côte d'Azur University : Reviewer

A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail

Partenaires

Thesis prepared in the laboratory IMEP-LaHC ( Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et de Caractérisation, and the Korea University supervised by Francis BALESTRA & Jae Woo LEE, supervisors.

Date of update November 28, 2023

Grenoble site
Grenoble INP - Minatec : 3, Parvis Louis Néel - CS 50257 - 38016 Grenoble Cedex 1

Chambery site
Université Savoie Mont Blanc - Rue Lac de la Thuile, Bat. 21 - 73370 Le Bourget du Lac