Exploration and integration of new devices in a 3D sequential stacking technology

Defense of doctoral thesis by Ayoub BOUTAYEB, for the  University  Grenoble Alpes, speciality " NANO ELECTRONIC & NANO TECHNOLOGIES ";

Keywords :
SOI MOSFET, TCAD simulation, electrical characterization, eDMOS, transistor architecture and physics.

Abstract :
The race towards miniaturization began when circuit complexity increased, and a higher integration density was needed to follow Moore’s Law. This led to the emergence of parasitic effects, such as short-channel effects, which cause performance degradation. To address these challenges, new architectures were introduced, such as the SOI transistor and the trigate. However, another alternative for size reduction was discovered, involving 3D vertical stacking through 3D sequential layering (3DSL).

This PhD thesis focuses particularly on the analysis of SOI MOSFETs used in 3DSL CMOS image sensor (CIS) applications. This analysis is conducted through TCAD simulations and electrical characterization. The thesis has three main objectives: identifying and analyzing the behavior of SOI devices used in the STMicroelecronics 3DSL technology, demonstrating the functionality of Extended Drain MOSFET ”eDMOS” and analyzing its performance, and lastly understanding SOI-induced phenomena, such as floating body effects  


Jury members :