EZ-FET: an electrical characterization test vehicle for process optimization of low temperature SOI substrates and devices

Defense of doctoral thesis by Nada ZERHOUNI ABDOU , for the  University  Grenoble Alpes, speciality  " NANO ELECTRONIC ET NANO TECHNOLOGIES "

Keywords :  
Electrical characterization,Silicon-On-Insulator,EZ-FET,Parameters extraction,Electrical modelisation,Low temperature processes

Abstract :
In the recent years, SOI (Silicon-On-Insulator) substrates and devices have seen numerous developments, exploring a wide range of technologies, materials and processes for various applications, such as the 3D sequential integration. To keep pace with these rapid advancements, a fast and reliable electrical characterization test-vehicle is mandatory to develop the technological bricks. Traditional test architectures are the pseudo-MOSFET (metal-oxide-semiconductor field effect transistor), widely used for SOI substrates and the entirely fabricated fully-depleted SOI FDSOI transistor for both substrate and device characterization. Even though largely employed, both have limitations: the pseudo-MOSFET cannot be adapted for the front-gate while the FDSOI MOSFET fabrication is long and costly.
This thesis introduces the EZ-FET (easy MOSFET), a simple and innovative device that bridges the gap between the two classical characterization architectures. The EZ-FET is an FDSOI-like transistor, with only two lithography levels needed to define the active region and the front gate stack. It combines the fast, simple and cost-effective fabrication of the pseudo-MOSFET with the double-gated configuration of the FDSOI transistor.
Subsequent to optimizing the EZ-FET device and customizing the characterization techniques and methodologies to fit its unique configuration, we focus on its use for low-temperature (LT) processes. One of the main challenges at LT (below 500°C) is the formation of the source/drain (S/D) junctions. Two approaches were evaluated to outcome this challenge. The first option involves the use of an EZ-FET with undoped S/D, removing completely the need of any activation, but bringing up a modelling issue, resolved by the development of an adapted electrical model and parameters extraction methodology. The second approach consists of the activation of S/D dopants by laser annealing, rather than standard furnace, giving raise this time to processing challenges that will be handled and validated through electrical measurements thanks to the EZ-FET.
Furthermore, the efficiency of the optimized EZ-FET is demonstrated through the characterization of various technological splits of SOI substrates, highlighting its capability in providing fast and comprehensive feedback for SOI substrates and development of technological bricks of the gate stack.

Membres du jury :

• Irina IONICA , ASSISTANT PROFESSOR- HDR - Grenoble INP - UGA : Supervisor
• Jean-Pierre RASKIN,   FULL PROFESSEUR - Université Catholique de Louvain : Reviewer
• Marc BOCQUET, PROFESSOR  of UNIVERSITIES - Aix-Marseille Université : Reviewer
• Damien DELERUYELLE, PROFESSOR of UNIVERSITIES - INSA Lyon : Examiner
• Claire FENOUILLET-BERANGER, RESEARCH DIRECTOR - CEA CENTRE DE GRENOBLE : Examiner
• Frédéric ALLIBERT, ENGINEER - SOITEC : Examiner