PhD Defense of Carlos NAVARRO
" Investigation of Advanced FDSOI Devices and Applications to Capacitorless DRAM "
Tuesday, September 29, 2015 at 10:00
Abstract :
The main purpose of this study is to investigate some ultimate scaling e ffects in fully depleted SOI devices, the interaction between these eff ects and how they threat the future of the capacitorless memory cell. In particular, the extreme inter-gate coupling eff ect, the supercoupling, is addressed in devices su ffering from short-channel effects (SCE).
The reciprocal mechanism, the ampli cation of the front- and back-interface SCE through coupling, leading to the SCE overestimation, is also considered. In order to complete this task, experimental measurements and numerical TCAD simulations are performed.
The thesis work also inspects novel techniques to determine essential device parameters.
For instance, we present the multipurpose characterization by capacitance analysis on
gated p-i-n diodes and the basis to extend the geometrical magnetoresistance procedure
to Multi-Gate FETs like double- and triple-gate FinFETs.
Finally, some of the main challenges of floating body 1T-DRAM cells for future are investigated, paying especial attention to the MSDRAM. It is demonstrated how the retention time can be easily boosted by a proper biasing scheme and how the memory variability is expected to decrease by controlling the randomness of some better-known static parameters like the back-gate threshold voltage.
Key Words:
1T-DRAM, SOI, Caracterisation,
Members of the jury :
M. Bruno SAGNES - Institut d’Electronique et des Systèmes : Supevisor
M. Sorin CRISTOLOVEANU IMEP - INP Grenoble MINATEC : CoSupervisor
Mme Maryline BAWEDIN IMEP - INP Grenoble MINATEC : Co-Supervisor
M. François ANDRIEU - CEA-LETI Grenoble : Co-Supervisor
M. Francisco GAMIZ - Universidad de Granada : Examiner
M. Fabien PASCAL - Institut d’Electronique et des Systèmes : Reviewer
M. Viktor SVERDLOV - Institute for Microelectronics : Rapporteur
M. Yong-Tae KIM Korea - Institute of Science and Technology : Rapporteur
M. Frédéric MARTINEZ - Institut d’Electronique et des Systèmes : Guest
Abstract :
The main purpose of this study is to investigate some ultimate scaling e ffects in fully depleted SOI devices, the interaction between these eff ects and how they threat the future of the capacitorless memory cell. In particular, the extreme inter-gate coupling eff ect, the supercoupling, is addressed in devices su ffering from short-channel effects (SCE).
The reciprocal mechanism, the ampli cation of the front- and back-interface SCE through coupling, leading to the SCE overestimation, is also considered. In order to complete this task, experimental measurements and numerical TCAD simulations are performed.
The thesis work also inspects novel techniques to determine essential device parameters.
For instance, we present the multipurpose characterization by capacitance analysis on
gated p-i-n diodes and the basis to extend the geometrical magnetoresistance procedure
to Multi-Gate FETs like double- and triple-gate FinFETs.
Finally, some of the main challenges of floating body 1T-DRAM cells for future are investigated, paying especial attention to the MSDRAM. It is demonstrated how the retention time can be easily boosted by a proper biasing scheme and how the memory variability is expected to decrease by controlling the randomness of some better-known static parameters like the back-gate threshold voltage.
Key Words:
1T-DRAM, SOI, Caracterisation,
Members of the jury :
M. Bruno SAGNES - Institut d’Electronique et des Systèmes : Supevisor
M. Sorin CRISTOLOVEANU IMEP - INP Grenoble MINATEC : CoSupervisor
Mme Maryline BAWEDIN IMEP - INP Grenoble MINATEC : Co-Supervisor
M. François ANDRIEU - CEA-LETI Grenoble : Co-Supervisor
M. Francisco GAMIZ - Universidad de Granada : Examiner
M. Fabien PASCAL - Institut d’Electronique et des Systèmes : Reviewer
M. Viktor SVERDLOV - Institute for Microelectronics : Rapporteur
M. Yong-Tae KIM Korea - Institute of Science and Technology : Rapporteur
M. Frédéric MARTINEZ - Institut d’Electronique et des Systèmes : Guest
Partenaires
Thesis prepared in the laboratory IMEP-LaHC (Institut de Microélectronique, Electromagnétisme, Photonique – Laboratoire Hyperfréquences et Caractérisation) supervised by M. Bruno SAGNES - Institut d’Electronique et des Systèmes and M. Sorin CRISTOLOVEANU- IMEP - INP Grenoble MINATEC .
Documents to download
Date infos
Thesis defense of Carlos NAVARRO for a doctoral thesis at the University of Grenoble, Nano Electronics and Nanotechnologies speciality, entitled:
Location infos
Auditorium M001-Grenoble INP - Phelma 3 Parvis Louis Néel - CS 50257
38016 Grenoble Cedex 01
Contact
M. Sorin CRISTOLOVEANU
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