PhD defense of Petros SIDERIS

Abstract :
As an alternative to the scaling-down of transistor feature-size in order to keep up the Moore’s law, three dimensional (3-D) integration technologies offer higher integration density,lower power consumption and provide a unique platform for heterogeneous integration of different active-layer materials through the vertical stacking of integrated circuit tiers. 3-D Sequential Integration, (also named 3-D monolithic integration or 3-D VLSI), is a type of 3D integration scheme, where the multiple stacked tiers are fabricated sequentially on top of each
other on the same wafer. Each tier consists of active and BEOL layers insulated by interlayer dielectric (ILD) layers. The fundamental property that differentiates this technology is the very close distance between the 2 (or more) layers which introduces very small parasitic capacitances allowing digital signals to have a high frequency while at the same time being generated with a low energy.
As a result, 3-D Sequential Integration brings new possibilities for mixed architectures with performances in both speed and low power consumption that cannot be easily met with other 3-D technologies schemes (TSV, copper to copper bonding etc.). However, the high frequency signals, the spatial localization, the strong interconnection density can all be a major source of interference between stacked tiers, modulating the expected behavior of devices as well as adding noise.
Therefore solutions and techniques have to be found in order to limit these effects. This work, aims to respond to this challenge and ensure the technology robustness. The impact of the
electromagnetic and noise interference between stacked tiers in 3-D Sequential Integration technology is thoroughly investigated in this work at both device and circuit level. To accomplish that, the most critical digital, analog and mixed-signal/RF designs have been selected to construct monolithic 3-D circuits. Experiments in conjunction with TCAD simulations reveal the coupling mechanisms responsible for the electromagnetic and noise propagation between stacked tiers.
Additionally, the strength of the propagated signals is assessed and its impact on the device/circuit performance is deeply explored.This study also examines the impact of 3-D Sequential Integration is examined on the performance of a CMOS Image Sensor (CIS) partitioned in different tiers. The CIS serves as an ideal case study of the coupling effects as it consists of highly sensitive parts to noise while it presents also an extremely appealing use of 3DSI to the semiconductor industry. The most critical figures of merit are therefore analyzed at a pixel level to ensure the normal operation of the circuit. Lastly, a comprehensive modeling of inter-tier coupling effects is presented. The models predict accurately the impact of layout effects on the inter-tier capacitive coupling between active devices, and can be integrated in SPICE tools to analyze complex and large-scale monolithic 3-D circuits, merging the gap between pre- and post-layout simulations

Jury members

• Dr. Gilles SICARD, Research Engineer, CEA-Leti, Grenoble : Superviser
• Dr. Perrine BATUDE, Research Engineer, CEA -Leti, Grenoble : Co-supervisor
• Dr. Christoforos THEODOROU , Researcher, IMEP-LAHC, Grenoble : Co-supervisor
• Pr. Per-Erik HELLSTROM, Professor of Universities, KTH, Stockholm, Sweden : Reviewer
• Pr Cristell MANEUX, Professor of  Universities, IMS, Bordeaux : Reviewer
• Dr Gérard GHIBAUDO, Research Director, IMEP-LAHC, Grenoble : Examiner
• Pr Pierre MAGNAN, Professor of Universities, ISAE, Toulouse : Examiner