PhD Defense of Renan LETHIECQ

High density integration in advanced CMOS technology, such as STMicroelectronics’ 28 nm UTBB FD-SOI technology, leads to elevated power density. This results in an increase of the local or global temperature which could cause dysfunction of the system, or even lead to its destruction by thermal runaway. In this context, we present innovative solutions for the “ robust integration regarding the electro-thermal activity following different scaling factors within the scope of integrated circuits development ”. Thus, we studied, at first, structures with dual source contact enabling : (i) in-situ heating in MOS transistors (temperature elevation up to hundreds of Kelvin degrees) ; (ii) performance recovery of these transistors by local annealing (MOSFET’s threshold voltage return to its typical value) ; (iii) creation of OTP memory dots (use of an electromigration effect inside the silicide) and (iv) temperature self-regulation of the transistors (utilisation of an integrated temperature sensor). Secondly, we developed a new low power temperature sensor (1 mV.K-1 slope for the output voltage and power of the order of picowatt) and its integration within a circuit using another transistor enabling electro-thermal behavior modification of the circuit. All our electronics structures were fabricated on 28 nm UTBB FD-SOI silicon demonstrators and measured. To carry out our work, we relied on some software for electro-thermal simulations. Their adaptation to our needs has been a third line of work.
 

• Philippe GALY - RESEARCHER ENGINEER  HDR  - ST Microelectronics Crolles : Supervisor
• Florin UDREA - PROFESSOR - University of Cambridge - United Kingdom : Reviewer
• Françis CALMON - PROFESSOR OF UNIVERSITIES  - University of Lyon : Reviewer
• Dominique PLANSON - PROFESSEUR OF UNIVERSITIES- University of Lyon : Examiner
• Nathalie LABAT - PROFESSEUR  OF UNIVERSITIES - University of Bordeaux : Examiner