PhD defense of Sotirios ATHANASIOU

The thesis main objective is the design of protection against electrostatic discharge (ESD), for deep submicron (DSM)  state-of-the-art fully depleted silicon-on-insulator technology (FDSOI  ). This requires the ESD characterization of existing elementary 
devices and design of new FDSOI devices.
The detailed characterization  of the physical mechanisms and device performance will be conducted at  IMEP which has adequate facilities and scientific competence in this 
field. It will then be necessary to make choices for ESD protection  strategies based on circuit applications by STMicroelectronics. An  ambitious approach aims to develop novel SOI components used for ESD  protection. This part of the work will be performed under the  responsibility of IMEP as it has has recently invented and published  several types of revolutionary transistors Z 2-FET, TFET and BET-FET. 
It will be necessary to understand the fabrication process technology  of STMicroelectronics. In this framework, 3D simulation of the  technology will be performed on TCAD software for 28nm FDSOI and  future technologies. Firstly it will embrace all the possibilities  inherent in the creation components to Boston in the specific  technology and then this preliminary study will provide structures for  ESD simulation configurations.
Physical simulation, with TCAD tools of  the semiconductor will be used to study more precisely the behavior of  the elementary components of ESD protection. Collaboration with the  IMEP is essential for the identification and analysis of the physical  mechanisms governing device operation.
In particular, the main  objective is to integrate ESD protection and evaluate its 
effectiveness and design. It will also be possible to perform  mixed-mode simulation to better analyse the effects of the 3D  structure (corner effects, depolarization of substrate) and evaluate  the influence of trigger circuits associated with this protection. 
Optimizing the implementation of ESD protection will then be possible  . Having studied from a theoretical point of view and numerical  simulation, ESD protection cells and trigger circuits associated with  the ESD protection strategy, qualification on silicon will be applied.  This will be done by a test vehicle in the chosen SOI technology, and  electrical characterization of the structures and protection networks 
will follow. Finally, the ESD performance will be analyzed to provide  optimization of the design and choice of ESD protection strategy based  on targeted applications.

 

 Key-words:
FD-SOI, Advanced CMOS, Electrical characterization, TCAD, ESD, Fabrication