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Seminar of Konstantinos ZEKENTES

“4H-SiC Trenched & Implanted Vertical JFETs (TI-VJFETs)”
Thursday, May 12nd, 2016  from 1:00 to 2:00 pm


SiC JFETs may have the lowest overall losses of switching devices and can operate at temperatures over 400°C. Over different JFET designs the trenched and implanted (TI) gate vertical JFET is very attractive since it may have the lowest on-resistance and its fabrication does not require epitaxial overgrowth or multiple angled ion implantations. The effort for developing high power 4H-SiC JFETs will be presented. Analytical and TCAD modeling, edge termination optimization, lithography approach and device parameter extraction from I-V measurements are some of the issues which will be addressed.

Dr. Konstantinos ZEKENTES received his undergraduate degree in Physics, from the University of Crete, Greece, and his Ph.D., in Physics of Semiconductors, from the University of Montpellier, France. He is currently a Senior Researcher with the Microelectronics Research Group (MRG) of the Foundation for Research and Technology-Hellas (FORTH) in Heraklion, Crete, Greece and since April 2016 visiting researcher in IMEP-LAHC.
 The objective of his work is to coordinate and supervise the MRG’s effort for the development of SiC-related technology for elaborating high power/high frequency devices as well as SiC-based 1D devices. Dr. Zekentes has more than hundred seventy journal and conference publications and one US patent.


by Konstantinos ZEKENTES
Microelectronics Research Group, Foundation for Research and Technology-Hellas
Heraklion, Crete.
Date infos
Open to all : teachers, students, researchers, administrative, technicians

Location infos
Amphi M001, PHELMA, Bât. INP, Minatec
3, parvis Louis Néel - 38000 Grenoble